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WCDMA Quasi-Direct Modulator
with VGA and PA Driver
Table 2. Register Power-Up Default States (f REF = 19.2MHz, f RF = 1950MHz)
RFM
RFR
OPCTRL
REGISTER
DEFAULT
9750 dec
4050 hex
(80 dec for ÷ R)
197D hex
ADDRESS
0010 b
0000 b
0100 b
FUNCTION
Main-divider ratio register
Reference-divider register
Operational control settings
Table 3. Operation Control Register (OPCTRL) Bit Assignments
BIT
BIT NAME
POWER-UP STATE
LOCATION
FUNCTION
(0 = LSB)
Setting this bit to zero shuts down everything except the serial interface
SHDN
1
0
and registers, which retain their values. It is overridden by a logic-low on
the SHDN pin.
If bit is set to 1, this leaves the GmC filters and the servo loop ON when
IDLE_PRG
0
1
the IDLE pin goes LOW. If bit is set to zero, the GmC filters shut off when
the IDLE pin goes LOW.
—
GmC_EN
PLL_EN
VCO_EN
PA_RF_IF_EN
X2_EN
MPL
PRD_Bias
OUT_Bias
1
1
1
1
1
0
1
0
0
2
3
4
5
6
7
8
9
10
Leave in power-up state.
Setting this bit to zero bypasses GmC filters.
Setting this bit to zero shuts off the RF PLL.
Setting this bit to zero shuts off the RF VCO.
Setting this bit to zero shuts off the PA driver, RF upconverter, and IF
modulator sections.
Setting this bit to 1 enables the X2 multiplier for use in the REF divider
section when TCXO frequency is 13MHz.
Maximum power level setting: 1 = +6dBm; 0 = +3dBm
Predriver bias: 0 = -25%; 1 = nominal
Output bias: 0 = nominal; 1 = +30%
A 2-bit word sets the RF charge-pump current as follows:
0 0 = 1000μA
RCP1, RCP0
11
12, 11
0 1 = 1500μA
1 0 = 2000μA
1 1 = 2500μA
A 2-bit word sets the Ameliorator current as follows:
0 0 = Off
AML1, AML0
00
14, 13
0 1 = Low (nominal)
1 0 = Mid
1 1 = High
These bits are used in DC offset trimming mode, where DC_TRM = 1.
DC_TRM
0
15
Setting this bit to 1 enables the DC offset trimming mode.
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